US 9,812,554 B2
Method for manufacturing a semiconductor device with increased breakdown voltage
Tomoyuki Sakuma, Nonoichi Ishikawa (JP); Shinya Sato, Nonoichi Ishikawa (JP); Noboru Yokoyama, Kanazawa Ishikawa (JP); and Akihiro Shimada, Kanazawa Ishikawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Minato-ku, Tokyo (JP)
Filed on Jan. 19, 2016, as Appl. No. 15/786.
Claims priority of application No. 2015-173209 (JP), filed on Sep. 2, 2015.
Prior Publication US 2017/0062585 A1, Mar. 2, 2017
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/266 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/66666 (2013.01) [H01L 21/266 (2013.01); H01L 21/3065 (2013.01); H01L 29/0634 (2013.01); H01L 29/4236 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a first opening in a second semiconductor layer of a first conductivity type, the second semiconductor layer being provided on a first semiconductor layer of the first conductivity type, the first opening extending in a second direction into the second semiconductor layer from an upper surface of the second semiconductor layer, a dimension in a third direction of the first opening at the upper surface being greater than a dimension in the third direction of a lower part of the first opening, the second direction being perpendicular to a first direction from the first semiconductor layer toward the second semiconductor layer, the third direction being perpendicular to the first direction and the second direction;
ion-implanting an impurity of a second conductivity type into a side surface of the lower part of the first opening; and
forming a third semiconductor layer of the second conductivity type in an interior of the first opening.