patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate;

conformally depositing a dummy spacer layer over surfaces of gate structures and the fins;

planarizing a dielectric fill formed over the gate structures and the fins to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures;

forming channels by removing the dummy spacer layer along the sidewalls of the gate structures, the fins being protected by the dielectric fill;

forming a spacer by filling the channels with a spacer material;

removing the dielectric fill and the dummy spacer layer to expose the fins; and

forming source and drain regions between the gate structures on the fins.