US 9,812,553 B1
Unipolar spacer formation for finFETs
Kangguo Cheng, Schenectady, NY (US); Peng Xu, Guilderland, NY (US); and Jie Yang, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed on Jul. 21, 2016, as Appl. No. 15/216,189.
Int. Cl. H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 21/308 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 16 Claims
OG exemplary drawing
1. A method for forming a spacer for a semiconductor device, comprising:
patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate;
conformally depositing a dummy spacer layer over surfaces of gate structures and the fins;
planarizing a dielectric fill formed over the gate structures and the fins to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures;
forming channels by removing the dummy spacer layer along the sidewalls of the gate structures, the fins being protected by the dielectric fill;
forming a spacer by filling the channels with a spacer material;
removing the dielectric fill and the dummy spacer layer to expose the fins; and
forming source and drain regions between the gate structures on the fins.