US 9,812,552 B2
Methods for fabricating semiconductor devices
Hwi-Chan Jun, Yongin-si (KR); Heon-Jong Shin, Yongin-si (KR); and Jae-Ran Jang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Hwi-Chan Jun, Yongin-si (KR); Heon-Jong Shin, Yongin-si (KR); and Jae-Ran Jang, Suwon-si (KR)
Filed on Apr. 6, 2015, as Appl. No. 14/679,166.
Claims priority of application No. 10-2014-0182970 (KR), filed on Dec. 18, 2014.
Prior Publication US 2016/0181399 A1, Jun. 23, 2016
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/66553 (2013.01) [H01L 21/28238 (2013.01); H01L 21/76816 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 21/823437 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
forming a gate structure on a substrate, the gate structure extending longitudinally in a first direction in plan view;
forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively;
partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern; and
replacing at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with a conductive pattern,
wherein the conductive pattern has a first width in the first direction adjacent the gate structure and has a second width in the first direction adjacent a medial point of the conductive pattern along a second direction that is a transverse direction of the gate structure, and the first width is greater than the second width.