US 9,812,551 B2
Method of forming the gate electrode of field effect transistor
Neng-Kuo Chen, Sinshih Township (TW); Clement Hsingjen Wann, Carmel, NY (US); Yi-An Lin, Taipei (TW); Chun-Wei Chang, Taoyuan (TW); and Sey-Ping Sun, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 21, 2017, as Appl. No. 15/437,962.
Application 15/437,962 is a division of application No. 13/572,494, filed on Aug. 10, 2012, granted, now 9,589,803.
Prior Publication US 2017/0162669 A1, Jun. 8, 2017
Int. Cl. H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/3212 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate comprising a dummy gate electrode having a sidewall, a source/drain (S/D) region, a spacer on the sidewall distributed between the dummy gate electrode and the S/D region, and an isolation feature;
depositing a contact etch stop layer (CESL) over the dummy gate electrode, the S/D region and the spacer;
depositing an interlayer dielectric (ILD) layer over the CESL;
performing a first chemical mechanical polishing (CMP) using a first slurry to expose the CESL over the dummy gate electrode;
performing a second CMP using a second slurry to expose the dummy gate electrode;
removing an upper portion of the CESL and an upper portion of the spacer; and
performing a third CMP using the first slurry to expose the CESL over the S/D region, wherein, following the third CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially co-planar with a top surface of the dummy gate electrode.