| US 9,812,547 B2 | ||
| Semiconductor device having fin-shaped semiconductor layer | ||
| Fujio Masuoka, Tokyo (JP); and Hiroki Nakamura, Tokyo (JP) | ||
| Assigned to UNISANTIS ELECTRONICS SINGAPORE PTE. LTD., Singapore (SG) | ||
| Filed by Unisantis Electronics Singapore Pte. Ltd., Singapore (SG) | ||
| Filed on Mar. 23, 2017, as Appl. No. 15/467,627. | ||
| Application 15/467,627 is a continuation of application No. 15/143,732, filed on May 2, 2016, granted, now 9,640,628. | ||
| Application 15/143,732 is a continuation of application No. PCT/JP2014/053746, filed on Feb. 18, 2014. | ||
| Prior Publication US 2017/0194453 A1, Jul. 6, 2017 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/00 (2006.01); H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01) | ||
| CPC H01L 29/4966 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823487 (2013.01); H01L 27/0886 (2013.01); H01L 27/10879 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78642 (2013.01)] | 4 Claims |
| 1. A semiconductor device, comprising:
a fin-shaped semiconductor layer on a semiconductor substrate;
a first insulating film around the fin-shaped semiconductor layer;
a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer;
a first gate insulating film around the pillar-shaped semiconductor layer;
a gate electrode formed of metal and around the first gate insulating film;
a gate line formed of metal connected to the gate electrode, and extending in a direction orthogonal to the fin-shaped semiconductor
layer, and
the first gate insulating film being around and under the gate electrode and the gate line;
a second gate insulating film around an upper side wall of the pillar-shaped semiconductor layer; and
a first contact around the second gate insulating film and formed of a second metal,
the gate electrode and the gate line having a top surface and a bottom surface, the top surface of the gate electrode and
the gate line having a larger area than the bottom surface of the gate electrode and the gate line; and
an upper portion of the first contact connected to an upper portion of the pillar-shaped semiconductor layer.
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