US 9,812,546 B2
Tungsten gates for non-planar transistors
Sameer S. Pradhan, Portland, OR (US); Daniel B. Bergstrom, Lake Oswego, OR (US); Jin-Sung Chun, Hillsboro, OR (US); and Julia Chiu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 9, 2017, as Appl. No. 15/401,965.
Application 15/401,965 is a continuation of application No. 14/860,336, filed on Sep. 21, 2015, granted, now 9,637,810.
Application 14/860,336 is a continuation of application No. 13/993,330, granted, now 9,177,867, issued on Nov. 3, 2015, previously published as PCT/US2011/054294, filed on Sep. 30, 2011.
Prior Publication US 2017/0117378 A1, Apr. 27, 2017
Int. Cl. H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); C23C 14/06 (2006.01); H01L 29/417 (2006.01); H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/4966 (2013.01) [C23C 14/0635 (2013.01); C23C 14/0652 (2013.01); H01L 21/28088 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 12 Claims
OG exemplary drawing
1. An integrated circuit (IC) structure, comprising:
a fin having a source and a drain, wherein the fin comprises silicon;
a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises:
a gate dielectric on the fin, wherein the gate dielectric comprises hafnium, silicon, and oxygen;
an NMOS gate electrode on the gate dielectric, wherein the NMOS gate electrode comprises:
a first layer on the gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon;
a second layer on the first layer, wherein the second layer comprises titanium; and
a third layer on the second layer, wherein the third layer comprises tungsten;
sidewalls on opposing sides of the NMOS gate electrode;
a capping structure over the NMOS gate electrode, wherein the capping structure comprises silicon and nitrogen;
a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen; and
a contact extending through the dielectric layer to one of the source and the drain.