US 9,812,543 B2
Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
Tek Po Rinus Lee, Malta, NY (US); Jinping Liu, Ballston lake, NY (US); and Ruilong Xie, Niskayuna, NY (US)
Assigned to GLOBALFOUNDRIES INC., Grand Cayman (KY)
Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed on Mar. 4, 2016, as Appl. No. 15/60,761.
Prior Publication US 2017/0256624 A1, Sep. 7, 2017
Int. Cl. H01L 21/266 (2006.01); H01L 29/47 (2006.01); H01L 29/40 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/285 (2006.01)
CPC H01L 29/47 (2013.01) [H01L 21/266 (2013.01); H01L 21/28518 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 29/401 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method comprising:
providing a substrate having an n-FET region and a p-FET region separated by a shallow trench isolation (STI) region, each of the n-FET and p-FET regions including a gate between source/drain regions;
forming an interlayer dielectric (ILD) over the substrate, with trenches formed through the ILD down to the source/drain regions;
applying a mask over the n-FET region;
implanting a dopant into the p-FET region source/drain regions through the trenches in the ILD;
selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked;
removing the mask;
depositing a titanium-based metal in the trenches over the n-FET and p-FET region source/drain regions; and
microwave annealing.