US 9,812,542 B2
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
Daniel E. Grupp, Palo Alto, CA (US); and Daniel J. Connelly, Redwood City, CA (US)
Assigned to Acorn Technologies, Inc., La Jolla, CA (US)
Filed by Acorn Technologies, Inc., La Jolla, CA (US)
Filed on Aug. 30, 2016, as Appl. No. 15/251,210.
Application 13/022,522 is a division of application No. 12/197,996, filed on Aug. 25, 2008, granted, now 7,884,003, issued on Feb. 8, 2011.
Application 12/197,996 is a division of application No. 11/181,217, filed on Jul. 13, 2005, granted, now 7,462,860, issued on Dec. 9, 2008.
Application 15/251,210 is a continuation of application No. 15/048,877, filed on Feb. 19, 2016.
Application 15/048,877 is a continuation of application No. 13/552,556, filed on Jul. 18, 2012, granted, now 9,425,277, issued on Aug. 23, 2016.
Application 13/552,556 is a continuation of application No. 13/022,522, filed on Feb. 7, 2011, granted, now 8,431,469, issued on Apr. 30, 2013.
Application 11/181,217 is a continuation of application No. 10/217,758, filed on Aug. 12, 2002, granted, now 7,084,423, issued on Aug. 1, 2006.
Prior Publication US 2016/0372564 A1, Dec. 22, 2016
Int. Cl. H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 29/08 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01); H01L 29/812 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/872 (2006.01); H01L 29/80 (2006.01)
CPC H01L 29/456 (2013.01) [H01L 21/28537 (2013.01); H01L 29/0895 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01); H01L 29/66143 (2013.01); H01L 29/66643 (2013.01); H01L 29/78 (2013.01); H01L 29/7839 (2013.01); H01L 29/806 (2013.01); H01L 29/812 (2013.01); H01L 29/872 (2013.01); H01L 29/785 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electrical junction comprising an interface layer disposed between a contact metal and a semiconductor, the semiconductor comprising a source or drain of a transistor, the interface layer comprising a metal oxide separation layer and a monolayer passivation layer and configured to provide a specific contact resistivity between the contact metal and the semiconductor of less than 1 Ω·μm2, wherein the monolayer passivation layer is a monolayer of arsenic.