US 9,812,540 B2
Enhanced switch device and manufacturing method therefor
Kai Cheng, Jiangsu (CN)
Assigned to ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
Appl. No. 14/395,338
Filed by Enkris Semiconductor, Inc., Jiangsu (CN)
PCT Filed Mar. 29, 2013, PCT No. PCT/CN2013/073432
§ 371(c)(1), (2) Date Oct. 17, 2014,
PCT Pub. No. WO2013/155929, PCT Pub. Date Oct. 24, 2013.
Claims priority of application No. 2012 1 0118172 (CN), filed on Apr. 20, 2012.
Prior Publication US 2015/0053921 A1, Feb. 26, 2015
Int. Cl. H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/4238 (2013.01) [H01L 21/28264 (2013.01); H01L 29/401 (2013.01); H01L 29/4925 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 29/2003 (2013.01); H01L 29/49 (2013.01)] 20 Claims
OG exemplary drawing
1. An enhancement mode switching device, comprising:
a substrate;
a nitride transistor structure arranged on the substrate;
a first dielectric layer formed on the nitride transistor structure, wherein a gate region and two ohmic contact regions respectively located at two sides of the gate region are defined on the first dielectric layer, and each of the two ohmic contact regions is through the first dielectric layer;
a groove formed in the gate region;
p-type semiconductor material formed in the groove; and
a source electrode and a drain electrode located at the two ohmic contact regions,
wherein, the groove is partially through the first dielectric layer and the p-type semiconductor material directly contacts, at the bottom of the groove, the first dielectric layer which separates the p-type semiconductor material from the nitride transistor structure, or
wherein, the groove is completely through the first dielectric layer and does not extend into the nitride transistor structure, and the device comprises further second dielectric layer formed in the groove completely through the first dielectric layer under the p-type semiconductor material.