US 9,812,539 B2
Semiconductor devices having buried contact structures
Yong-Jun Kim, Suwon-si (KR); Sung-In Kim, Hwaseong-si (KR); Jung-Woo Song, Hwaseong-si (KR); Jae-Rok Kahng, Seoul (KR); and Dae-Won Kim, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR)
Filed on Dec. 8, 2015, as Appl. No. 14/962,003.
Claims priority of application No. 10-2014-0181943 (KR), filed on Dec. 17, 2014.
Prior Publication US 2016/0181385 A1, Jun. 23, 2016
Int. Cl. H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 27/24 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/74 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 45/00 (2006.01); H01L 21/285 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 21/743 (2013.01); H01L 21/76897 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 29/66621 (2013.01); H01L 21/28518 (2013.01); H01L 27/10855 (2013.01); H01L 27/10888 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising: a substrate defining a gate trench therein;
a buried gate structure in the gate trench and at least filling the gate trench to a top portion thereof, the buried gate structure including a gate insulation layer pattern, a gate electrode and a capping layer pattern;
first and second impurity regions in the substrate on opposite sides of the buried gate structure, at least a portion of each of the first and second impurity regions facing a sidewall of the buried gate structure; and
first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures facing a sidewall of the buried gate structure; and
an isolation layer on the substrate, wherein a top surface of the isolation layer is substantially coplanar with top surfaces of the first and second buried contact structures,
wherein top surfaces of the first and second buried contact structures are substantially coplanar with that of the buried gate structure;
wherein bottom surfaces of the first and second impurity regions are substantially coplanar with a bottom surface of the gate electrode of the buried gate structure; and
wherein bottom surfaces of the first and second impurity regions are flat.