US 9,812,538 B2
Buried bus and related method
Hugo Burke, Llantrisant (GB); and Ling Ma, Redondo Beach, CA (US)
Assigned to Infineon Technologies Americas Corp., El Segundo, CA (US)
Filed by Infineon Technologies Americas Corp., El Segundo, CA (US)
Filed on Dec. 1, 2015, as Appl. No. 14/955,299.
Prior Publication US 2017/0154970 A1, Jun. 1, 2017
Int. Cl. H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 21/76877 (2013.01); H01L 29/495 (2013.01); H01L 29/4991 (2013.01); H01L 29/7827 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate having a gate electrode in a gate trench;
a buried bus in said semiconductor substrate, said buried bus having a bus conductive filler in a bus trench;
a dielectric liner in said gate trench and said bus trench; and
an adhesion promotion layer in said bus trench and interposed between said bus conductive filler and said gate electrode,
wherein said bus conductive filler is electrically coupled to said gate electrode.
 
10. A method of forming a semiconductor structure, said method comprising:
forming a gate trench and a bus trench in a semiconductor substrate, said gate trench connected to said bus trench;
forming a dielectric liner in said gate trench and said bus trench;
forming a gate electrode in said gate trench and said bus trench;
forming an opening in said gate electrode in said bus trench;
forming a bus conductive filler in said opening, thereby forming a buried bus; and
forming an adhesion promotion layer in said bus trench and interposed between said bus conductive filler and said gate electrode,
wherein said bus conductive filler is electrically coupled to said gate electrode.
 
18. A semiconductor structure, comprising:
a semiconductor substrate having a gate electrode in a gate trench;
a buried bus in said semiconductor substrate, said buried bus having a bus conductive filler in a bus trench; and
a dielectric layer over and in contact with said semiconductor substrate,
wherein said gate electrode extends to and terminates at a first surface of said dielectric layer, said first surface facing said semiconductor substrate,
wherein said bus conductive filler extends to and terminates at a second surface of said dielectric layer opposite said first surface,
wherein said gate trench runs perpendicular to said bus trench,
wherein said bus conductive filler is electrically coupled to said gate electrode.