US 9,812,536 B2
Reverse tone self-aligned contact
Ching-Feng Fu, Taichung (TW); Yu-Chan Yen, Taipei (TW); and Chia-Ying Lee, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 21, 2016, as Appl. No. 15/215,845.
Application 15/215,845 is a continuation of application No. 14/180,460, filed on Feb. 14, 2014, granted, now 9,412,656.
Prior Publication US 2016/0329406 A1, Nov. 10, 2016
Int. Cl. H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/08 (2006.01); H01L 29/267 (2006.01)
CPC H01L 29/41783 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/32115 (2013.01); H01L 21/76879 (2013.01); H01L 21/76897 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/267 (2013.01); H01L 29/4175 (2013.01); H01L 29/42364 (2013.01); H01L 29/45 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66606 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a pair of gate structures comprising a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode;
a source/drain region arranged within the substrate between the pair of gate structures;
insulating sidewall spacers arranged along opposing sides of the pair of gate structures;
an etch stop layer arranged along sidewalls of the pair of gate structures and over the source/drain region;
a dielectric layer over the insulating material, wherein the dielectric layer is laterally separated from the insulating sidewall spacers by the etch stop layer;
a source/drain contact arranged over the insulating material and the etch stop layer and separated from the sidewalls of the pair of gate structures by the etch stop layer, wherein the source/drain contact is electrically coupled to the source/drain region; and
wherein the etch stop layer has a bottom surface that contacts the source/drain region at a first interface that is above a bottom surface of the insulating sidewall spacers and a top surface that contacts the source/drain contact.