US 9,812,535 B1
Method for manufacturing a semiconductor device and power semiconductor device
Robert Haase, San Pedro, CA (US); and Martin Vielemeyer, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Nov. 29, 2016, as Appl. No. 15/363,740.
Int. Cl. H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/407 (2013.01) [H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/408 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A power semiconductor device, comprising:
a semiconductor substrate having a first side;
a trench formed in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate;
an insulation structure comprising:
at least a first insulation layer covering the bottom of the trench and extending from the bottom of the trench along the sidewall of the trench to the first side of the semiconductor substrate; and
a second insulation layer on the first insulation layer and extending along the first insulation layer to an upper end of the second insulation layer being recessed relative to the first side of the semiconductor substrate,
wherein the first insulation layer and the second insulation layer are comprised of different materials, and
wherein the upper end of the second insulation layer defines an upper end of a lower portion of the trench;
a lower conductive structure in the lower portion of the trench, wherein each of the first and the second insulation layers is arranged between the lower conductive structure and the semiconductor substrate; and
an upper conductive structure in an upper portion of the trench above the lower portion, wherein the first insulation layer is arranged between the upper conductive structure and the semiconductor substrate.