US 9,812,528 B2
Semiconductor device
Hiroshi Kono, Himeji Hyogo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Minato-ku, Tokyo (JP)
Filed on Sep. 15, 2015, as Appl. No. 14/855,255.
Claims priority of application No. 2015-052275 (JP), filed on Mar. 16, 2015.
Prior Publication US 2016/0276443 A1, Sep. 22, 2016
Int. Cl. H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/167 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/42364 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01); H01L 29/45 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a cell region;
a gate connection region; and
a cell end region provided between the cell region and the gate connection region,
the cell region including:
an n-type first SiC region provided at a first surface of a SiC substrate having the first surface and a second surface;
a p-type second SiC region provided between the first SiC region and the second surface;
a first region of an n-type third SiC region provided between the second SiC region and the second surface;
a p-type fourth SiC region provided at the first surface in the second SiC region and having a higher p-type impurity concentration than the second SiC region;
a gate insulating film provided on the second SiC region;
a first gate electrode provided on the gate insulating film;
a first electrode region of a first electrode provided on the first surface, the first electrode region contacting with the first SiC region and the fourth SiC region; and
a second electrode provided at the second surface,
the gate connection region including:
a field insulating film provided on the first surface and thicker than the gate insulating film;
a second gate electrode provided on the field insulating film; and
a p-type fifth SiC region provided between a second region of the third SiC region and the field insulating film, the fifth SiC region contacting with the first surface and having a peak p-type impurity concentration of 1×1018 cm−3 or more,
the cell end region including:
a p-type sixth SiC region connected to the fifth SiC region;
a p-type seventh SiC region provided at the first surface in the sixth SiC region and having a higher p-type impurity concentration than the sixth SiC region; and
a second electrode region of the first electrode contacting with the seventh SiC region,
wherein the p-type impurity concentration of the fifth SiC region is higher than the p-type impurity concentration of the second SiC region provided between the first gate electrode and the second surface,
a distance of a peak position of the p-type impurity concentration of the fifth SiC region from the first surface is equal to or greater than 0.1 μm and equal to or less than 0.3 μm, and
the depth of the fifth SiC region is less than the depth of the second SiC region.