US 9,812,524 B2
Nanowire transistor devices and forming techniques
Glenn A. Glass, Portland, OR (US); Kelin J. Kuhn, Alohoa, OR (US); Seiyon Kim, Portland, OR (US); Anand S. Murthy, Portland, OR (US); and Daniel B. Aubertine, North Plains, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on May 16, 2016, as Appl. No. 15/155,806.
Application 15/155,806 is a continuation of application No. 14/690,615, filed on Apr. 20, 2015, granted, now 9,343,559, issued on May 17, 2016.
Application 14/690,615 is a continuation of application No. 13/560,531, filed on Jul. 27, 2012, granted, now 9,012,284, issued on Apr. 21, 2015.
Application 13/560,531 is a continuation in part of application No. PCT/US2011/067225, filed on Dec. 23, 2011.
Prior Publication US 2016/0260802 A1, Sep. 8, 2016
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0676 (2013.01) [H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/7855 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
15. An integrated circuit (IC) comprising:
a first transistor above a substrate, the first transistor including a first channel region that includes a semiconductor material nanowire, the first transistor further including a first gate structure around the semiconductor material nanowire; and
a second transistor above the substrate, the second transistor including a second channel region that includes a semiconductor material fin, the second transistor further including a second gate structure adjacent three sides of the semiconductor material fin;
wherein at least one common horizontal plane passes through each of the semiconductor material nanowire and the semiconductor material fin, and
wherein the semiconductor material nanowire and the semiconductor material fin include relatively different material compositions.