US 9,812,507 B2
Semiconductor memory device
Masanori Komura, Mie (JP); and Takeshi Takagi, Mie (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Tokyo (JP)
Filed by TOSHIBA MEMORY CORPORATION, Minato-ku, Tokyo (JP)
Filed on Aug. 3, 2016, as Appl. No. 15/227,493.
Claims priority of provisional application 62/306,984, filed on Mar. 11, 2016.
Prior Publication US 2017/0263682 A1, Sep. 14, 2017
Int. Cl. H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 23/528 (2006.01)
CPC H01L 27/249 (2013.01) [H01L 23/528 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a semiconductor substrate which extends in first and second directions that intersect each other;
a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction;
a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and
a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines,
one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines,
the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells, and
the second films of two of the memory cells adjacent in the first direction being separated between the two memory cells.