| US 9,812,506 B1 | ||
| Nano-imprinted self-aligned multi-level processing method | ||
| Mac D. Apodaca, San Jose, CA (US); and Daniel Robert Shepard, North Hampton, NH (US) | ||
| Assigned to WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US) | ||
| Filed by Western Digital Technologies, Inc., San Jose, CA (US) | ||
| Filed on Apr. 13, 2016, as Appl. No. 15/98,253. | ||
| Int. Cl. H01L 47/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01) | ||
| CPC H01L 27/249 (2013.01) [H01L 27/2427 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1266 (2013.01); H01L 45/1683 (2013.01)] | 16 Claims |
| 1. A method comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
depositing a first plurality of layers in the first trench;
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
depositing a second plurality of layers in the second trench;
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate; and
depositing a third plurality of layers in the third trench, wherein the first portion has a first height, the second portion
has a second height and the third portion has a third height, and wherein the second height is less than the first height
and the third height is less than the second height.
|