US 9,812,504 B2
Electronic device
Tae-Young Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-Si (KR)
Filed by SK hynix Inc., Icheon-Si (KR)
Filed on Sep. 19, 2016, as Appl. No. 15/268,847.
Application 15/268,847 is a continuation of application No. 14/951,048, filed on Nov. 24, 2015, granted, now 9,450,021.
Claims priority of application No. 10-2015-0077166 (KR), filed on Jun. 1, 2015.
Prior Publication US 2017/0005139 A1, Jan. 5, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/24 (2006.01); H01L 45/00 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 11/56 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01)
CPC H01L 27/2463 (2013.01) [G06F 3/061 (2013.01); G06F 3/068 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0676 (2013.01); G11C 11/16 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/56 (2013.01); G11C 11/5607 (2013.01); G11C 11/5685 (2013.01); G11C 13/0002 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); H01L 27/224 (2013.01); H01L 43/08 (2013.01); H01L 45/08 (2013.01); H01L 45/085 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); G11C 2213/15 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
an array of semiconductor memory cells, each semiconductor memory cell comprising:
(1) a first variable resistance structure including a first material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the first material in response to a first control signal applied to the first material;
(2) a Magnetic Tunnel Junction (MTJ) structure comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer, the MTJ structure being coupled to the first variable resistance structure by having the first magnetic layer in contact with the first variable resistance structure, wherein the MTJ structure exhibits a first MTJ resistance state when magnetizations of the first and second magnetic layers are parallel to each other and a second, different MTJ resistance state when magnetizations of the first and second magnetic layers are anti-parallel to each other; and
(3) a second variable resistance structure including a second material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the second material in response to a second control signal applied to the second material, the second variable resistance structure being coupled to the MTJ structure by being in contact with the second magnetic layer; and
a circuit coupled to the array of semiconductor memory cells to control the first and second variable resistance structures and the MTJ structure within each cell to operate each cell in one of different combinations of resistance states of the MTJ structure and the first and second variable structures in each cell for storing data.