| US 9,812,503 B2 | ||
| Embedded non-volatile memory | ||
| Daniel R. Shepard, North Hampton, NH (US); Mac D. Apodaca, San Jose, CA (US); Thomas Michael Trent, Tucson, AZ (US); and James Juen Hsu, Saratoga, CA (US) | ||
| Assigned to HGST, Inc., San Jose, CA (US) | ||
| Filed by HGST, Inc., San Jose, CA (US) | ||
| Filed on Aug. 15, 2016, as Appl. No. 15/236,600. | ||
| Application 15/236,600 is a continuation of application No. 14/733,919, filed on Jun. 8, 2015, granted, now 9,431,460. | ||
| Application 14/733,919 is a continuation of application No. 14/306,801, filed on Jun. 17, 2014, granted, now 9,054,031, issued on Jun. 9, 2015. | ||
| Application 14/306,801 is a continuation of application No. 13/707,895, filed on Dec. 7, 2012, granted, now 8,786,023, issued on Jul. 22, 2014. | ||
| Claims priority of provisional application 61/630,297, filed on Dec. 8, 2011. | ||
| Claims priority of provisional application 61/632,393, filed on Jan. 20, 2012. | ||
| Prior Publication US 2016/0351627 A1, Dec. 1, 2016 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/04 (2006.01); H01L 21/8238 (2006.01); H01L 27/102 (2006.01) | ||
| CPC H01L 27/2463 (2013.01) [H01L 21/8238 (2013.01); H01L 27/04 (2013.01); H01L 27/1021 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/14 (2013.01); H01L 45/141 (2013.01); H01L 45/144 (2013.01); H01L 45/16 (2013.01); H01L 45/1683 (2013.01)] | 20 Claims |
| 1. A CMOS device, comprising:
a doped silicon substrate;
a doped epi silicon layer formed over the doped silicon substrate;
a first p-doped well disposed within the doped epi silicon layer;
an n-doped bitline coupled to the first p-doped well;
a second p-doped well disposed within the doped epi silicon layer; and
an n-doped well disposed within the doped epi silicon layer, wherein the second p-doped well and the n-doped well are coupled
together.
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