US 9,812,502 B2
Semiconductor memory device having variable resistance elements provided at intersections of wiring lines
Takuya Konno, Yokkaichi (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed by Toshiba Memory Corporation, Minato-ku (JP)
Filed on Mar. 22, 2016, as Appl. No. 15/77,026.
Claims priority of provisional application 62/212,056, filed on Aug. 31, 2015.
Prior Publication US 2017/0062527 A1, Mar. 2, 2017
Int. Cl. H01L 29/02 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01)
CPC H01L 27/2463 (2013.01) [G11C 13/0002 (2013.01); H01L 45/1608 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;
a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;
a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines;
a first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to one of the plurality of the second wiring lines, and
a second contact extending in the third direction, one end of the second contact being connected to one of the plurality of the first wiring lines,
the other end of the first contact and a surface intersecting the first direction of the first contact being covered by a first conductive layer, and
the other end of the second contact and a surface intersecting the second direction of the second contact being covered by a second conductive layer.