US 9,812,501 B2
Variable resistance memory devices and methods of manufacturing the same
Jin-Woo Lee, Hwaseong-si (KR); Youn-Seon Kang, Yongin-si (KR); Seung-Jae Jung, Suwon-si (KR); Hyun-Su Ju, Hwaseong-si (KR); and Masayuki Terai, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Jin-Woo Lee, Hwaseong-si (KR); Youn-Seon Kang, Yongin-si (KR); Seung-Jae Jung, Suwon-si (KR); Hyun-Su Ju, Hwaseong-si (KR); and Masayuki Terai, Suwon-si (KR)
Filed on Dec. 30, 2015, as Appl. No. 14/984,477.
Claims priority of application No. 10-2015-0000571 (KR), filed on Jan. 5, 2015.
Prior Publication US 2016/0197121 A1, Jul. 7, 2016
Int. Cl. H01L 27/24 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01)
CPC H01L 27/2463 (2013.01) [H01L 27/224 (2013.01); H01L 27/2409 (2013.01); H01L 43/12 (2013.01); H01L 45/1675 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A variable resistance memory device, comprising:
a plurality of first conductive layer patterns extending in a first direction;
a plurality of second conductive layer patterns over the plurality of first conductive layer patterns, the plurality of second conductive layer patterns extending in a second direction to cross the plurality of first conductive layer patterns; and
a plurality of lower cell structures formed at intersections of the plurality of first conductive layer patterns and the plurality of second conductive layer patterns, each of the plurality of lower cell structures including a lower switching element and a lower variable resistance element,
wherein the plurality of first conductive layer patterns, the plurality of second conductive layer patterns and the plurality of lower cell structures form a plurality of pattern structures, each of the plurality of pattern structures serving as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure of the variable resistance memory device,
wherein the first dummy pattern structure is formed on at least a first edge portion in the first direction, and a second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of a lower cell structure of the first dummy pattern structure, and
wherein the second dummy pattern structure is formed on at least a second edge portion in the second direction, and a first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of a lower cell structure of the second dummy pattern structure.