a plurality of first conductive layer patterns extending in a first direction;

a plurality of second conductive layer patterns over the plurality of first conductive layer patterns, the plurality of second conductive layer patterns extending in a second direction to cross the plurality of first conductive layer patterns; and

a plurality of lower cell structures formed at intersections of the plurality of first conductive layer patterns and the plurality of second conductive layer patterns, each of the plurality of lower cell structures including a lower switching element and a lower variable resistance element,

wherein the plurality of first conductive layer patterns, the plurality of second conductive layer patterns and the plurality of lower cell structures form a plurality of pattern structures, each of the plurality of pattern structures serving as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure of the variable resistance memory device,

wherein the first dummy pattern structure is formed on at least a first edge portion in the first direction, and a second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of a lower cell structure of the first dummy pattern structure, and

wherein the second dummy pattern structure is formed on at least a second edge portion in the second direction, and a first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of a lower cell structure of the second dummy pattern structure.