US 9,812,490 B2
Semiconductor device, manufacturing method thereof, and electronic apparatus
Kazuichiroh Itonaga, Tokyo (JP); and Machiko Horiike, Kanagawa (JP)
Assigned to Sony Corporation, Tokyo (JP)
Filed by Sony Corporation, Tokyo (JP)
Filed on Apr. 9, 2014, as Appl. No. 14/248,948.
Application 14/248,948 is a continuation of application No. 13/312,261, filed on Dec. 6, 2011, granted, now 8,742,524.
Claims priority of application No. 2010-279833 (JP), filed on Dec. 15, 2010.
Prior Publication US 2014/0217542 A1, Aug. 7, 2014
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); H04N 5/374 (2011.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/552 (2006.01); H01L 31/02 (2006.01)
CPC H01L 27/14647 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/552 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14603 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14638 (2013.01); H01L 27/14687 (2013.01); H04N 5/374 (2013.01); H01L 31/02002 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/8203 (2013.01); H01L 2224/92 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/3011 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device configured as a backside illuminated solid-state imaging device, comprising:
a stacked semiconductor device which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit, and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit, and in which the pixel array is formed in a first semiconductor substrate included as part of the first semiconductor chip unit,
wherein a laminated insulating layer is disposed on the first semiconductor substrate,
wherein the first semiconductor chip unit has a connection hole and a through connection hole which both are formed in the first semiconductor substrate and a concave portion which is formed in the laminated insulating layer,
wherein a first set of connection wirings is formed so as to be buried in the connection hole, the through connection hole and the concave portion and electrically connects the first and second semiconductor chip units to each other,
wherein the first set of connection wirings is a unitary structure,
wherein a surface of at least a part of the first set of connection wirings is higher than a surface of the laminated insulating layer in a first section, and
wherein the surface of the part of the first set of connection wirings is lower than the surface of the laminated insulating layer in a second section.