US 9,812,477 B2
Photodiode gate dielectric protection layer
Cheng-Hsien Chou, Tainan (TW); Wen-I Hsu, Tainan (TW); Tsun-Kai Tsao, Tainan (TW); Chih-Yu Lai, Tainan (TW); Jiech-Fun Lu, Madou Township (TW); and Yeur-Luen Tu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jun. 1, 2016, as Appl. No. 15/169,994.
Application 15/169,994 is a continuation of application No. 14/867,070, filed on Sep. 28, 2015, granted, now 9,412,781.
Application 14/867,070 is a continuation of application No. 13/948,217, filed on Jul. 23, 2013, granted, now 9,147,710, issued on Sep. 29, 2015.
Prior Publication US 2016/0276384 A1, Sep. 22, 2016
Int. Cl. H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 27/146 (2006.01); H01L 31/18 (2006.01)
CPC H01L 27/14614 (2013.01) [H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 31/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a photodetector disposed within a substrate;
a gate structure located over the substrate;
a gate dielectric protection layer disposed over the substrate and extending from along a sidewall of the gate structure to a location overlying the photodetector, wherein the gate dielectric protection layer comprises a lateral segment and a vertical segment protruding outward from an upper surface of the lateral segment and extending along the sidewall of the gate structure; and
wherein the gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.