US 9,812,469 B2
Array substrate having a plurality of gate electrode material lines, source-drain electrode material lines and first metal lines
Zhanfeng Cao, Beijing (CN); Feng Zhang, Beijing (CN); Bin Zhang, Beijing (CN); Xiaolong He, Beijing (CN); Jincheng Gao, Beijing (CN); Qi Yao, Beijing (CN); Zhengliang Li, Beijing (CN); and Xiangchun Kong, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on May 10, 2016, as Appl. No. 15/150,549.
Claims priority of application No. 2015 1 0379820 (CN), filed on Jul. 1, 2015.
Prior Publication US 2017/0005110 A1, Jan. 5, 2017
Int. Cl. H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01)
CPC H01L 27/124 (2013.01) [H01L 29/41733 (2013.01); H01L 29/42384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate comprising a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed,
wherein, overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.