US 9,812,466 B2
Semiconductor device
Tomoaki Atsumi, Kanagawa (JP); Masayuki Sakakura, Kanagawa (JP); Yoshitaka Yamamoto, Nara (JP); Jun Koyama, Kanagawa (JP); Tetsuhiro Tanaka, Kanagawa (JP); and Kazuki Tanemura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Aug. 4, 2015, as Appl. No. 14/817,709.
Claims priority of application No. 2014-162751 (JP), filed on Aug. 8, 2014; and application No. 2014-254710 (JP), filed on Dec. 17, 2014.
Prior Publication US 2016/0043110 A1, Feb. 11, 2016
Int. Cl. H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/1225 (2013.01) [H01L 29/78648 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit comprising a memory circuit;
a second circuit comprising a first output terminal and a second output terminal; and
a third circuit comprising a second memory circuit,
wherein the memory circuit comprises a first transistor comprising a first gate electrode, a second gate electrode, a first insulator, a second insulator, and a semiconductor,
wherein the first output terminal is connected to the first gate electrode and the second output terminal is connected to the second gate electrode,
wherein the first gate electrode comprises a region overlapping the semiconductor with the first insulator between the first gate electrode and the semiconductor,
wherein the second gate electrode comprises a region overlapping the semiconductor with the second insulator between the second gate electrode and the semiconductor,
wherein the second circuit is configured to apply a positive voltage to the second gate electrode when the first transistor is on, and apply zero voltage or a negative voltage to the second gate electrode when the first transistor is off,
wherein the third circuit comprises a second transistor comprising an electron trap layer formed on a same substrate as the first transistor, the third circuit being functionally connected to the first circuit, and
wherein the second insulator does not include the electron trap layer.