US 9,812,463 B2
Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
Rahul Sharangpani, Fremont, CA (US); Raghuveer S. Makala, Campbell, CA (US); Senaka Kanakamedala, Milpitas, CA (US); Fei Zhou, Milpitas, CA (US); Somesh Peri, San Jose, CA (US); Masanori Tsutsumi, Yokkaichi (JP); Keerti Shukla, Saratoga, CA (US); Yusuke Ikawa, Yokkaichi (JP); Kiyohiko Sakakibara, Yokkaichi (JP); and Eisuke Takii, Yokkaichi (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Plano, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Plano, TX (US)
Filed on Aug. 29, 2016, as Appl. No. 15/250,185.
Application 15/250,185 is a continuation in part of application No. 15/158,954, filed on May 19, 2016.
Claims priority of provisional application 62/313,234, filed on Mar. 25, 2016.
Prior Publication US 2017/0278859 A1, Sep. 28, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 27/11582 (2017.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 27/11573 (2017.01)
CPC H01L 27/11582 (2013.01) [H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02247 (2013.01); H01L 21/02326 (2013.01); H01L 27/11573 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory stack structure extending through the alternating stack and comprising a tunneling dielectric layer and a vertical semiconductor channel, wherein first portions of an outer sidewall of the tunneling dielectric layer contact proximal sidewalls of the insulating layers; and
charge trapping material portions located at each level of the electrically conductive layers, comprising a dielectric compound including silicon and nitrogen, and contacting second portions of the outer sidewall of the tunneling dielectric layer.