US 9,812,462 B1
Memory hole size variation in a 3D stacked memory
Liang Pang, Fremont, CA (US); Ashish Baraskar, Santa Clara, CA (US); Yanli Zhang, San Jose, CA (US); and Yingda Dong, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Plano, TX (US)
Filed by SanDisk Technologies LLC, Plano, TX (US)
Filed on Jun. 7, 2016, as Appl. No. 15/175,304.
Int. Cl. H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01)
CPC H01L 27/11582 (2013.01) [H01L 21/28282 (2013.01); H01L 27/1157 (2013.01); H01L 29/7926 (2013.01)] 11 Claims
OG exemplary drawing
1. An apparatus, comprising:
a plurality of layers in a stack, the plurality of layers comprising word line layers which are vertically spaced apart from one another by dielectric layers, the plurality of layers are adjacent to a local interconnect of the stack, the local interconnect extends through the stack; and
a set of memory holes which extend through the stack, each memory hole of the set of memory holes comprises a sidewall, and along the sidewall, a blocking oxide layer followed by a charge trapping layer, a tunnel oxide layer and a polysilicon channel layer, wherein the memory holes of the set of memory holes have diameters which are progressively smaller as a distance between the memory holes and the local interconnect is progressively larger and widths of the blocking oxide layers are relatively smaller when the distances are relatively smaller.