a plurality of layers in a stack, the plurality of layers comprising word line layers which are vertically spaced apart from one another by dielectric layers, the plurality of layers are adjacent to a local interconnect of the stack, the local interconnect extends through the stack; and

a set of memory holes which extend through the stack, each memory hole of the set of memory holes comprises a sidewall, and along the sidewall, a blocking oxide layer followed by a charge trapping layer, a tunnel oxide layer and a polysilicon channel layer, wherein the memory holes of the set of memory holes have diameters which are progressively smaller as a distance between the memory holes and the local interconnect is progressively larger and widths of the blocking oxide layers are relatively smaller when the distances are relatively smaller.