US 9,812,460 B1
NVM memory HKMG integration technology
Wei Cheng Wu, Zhubei (TW); and Chien-Hung Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 24, 2016, as Appl. No. 15/162,761.
Int. Cl. H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/11521 (2013.01) [H01L 27/11526 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/7831 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit (IC), comprising:
providing a substrate comprising a memory region and a logic region;
forming and patterning a floating gate layer and a control gate layer to form a pair of memory gate stacks within the memory region comprising control gate electrodes and floating gates and to form a sacrificial logic gate stack within the logic region;
replacing the sacrificial logic gate stack with a high-k dielectric layer and a metal layer to form a metal gate electrode within the logic region;
forming an inter-poly dielectric layer between the floating gate layer and the control gate layer;
forming a control gate spacer along the control gate electrodes; and
patterning the inter-poly dielectric layer and the floating gate layer within the memory region according to the control gate spacer to form an inter-poly dielectric and the floating gates.