US 9,812,459 B2
Embedded SRAM and methods of forming the same
Jhon Jhy Liaw, Zhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 17, 2016, as Appl. No. 15/46,150.
Application 15/046,150 is a division of application No. 13/922,097, filed on Jun. 19, 2013, granted, now 9,293,466.
Prior Publication US 2016/0163717 A1, Jun. 9, 2016
Int. Cl. H01L 27/11 (2006.01); H01L 29/32 (2006.01); G11C 11/412 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01)
CPC H01L 27/1104 (2013.01) [G11C 11/412 (2013.01); H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 21/324 (2013.01); H01L 21/76224 (2013.01); H01L 27/0886 (2013.01); H01L 27/1116 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/32 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7843 (2013.01); H01L 29/7847 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first gate stack in a first device region and a second gate stack in a second device region;
forming an implant blocking layer to cover the second device region, wherein the first device region is not covered by the implant blocking layer;
recessing a portion of a semiconductor region in the first device region to form a recess;
performing an amorphization implantation to form an amorphized region under the recess, wherein no amorphized region is formed in the second device region;
forming a strained capping layer over the first gate stack and the amorphized region;
performing an annealing to re-crystalize the amorphized region to form a re-crystallized region, wherein a first dislocation plane is formed in the re-crystallized region;
removing the strained capping layer and the implant blocking layer;
epitaxially growing a first source/drain region in the recess; and
forming a second source/drain region in the second device region and adjacent to the second gate stack, wherein the first source/drain region is a part of a multi-fin Fin Field Effect Transistor (FinFET), and wherein the second source/drain region is a part of a single-fin FinFET.