US 9,812,458 B2
Memory device and method for manufacturing the same
Daisuke Matsubayashi, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (JP)
Filed on Aug. 18, 2016, as Appl. No. 15/240,328.
Application 15/240,328 is a division of application No. 13/410,610, filed on Mar. 2, 2012, granted, now 9,425,107.
Claims priority of application No. 2011-052448 (JP), filed on Mar. 10, 2011; and application No. 2011-112648 (JP), filed on May 19, 2011.
Prior Publication US 2016/0358923 A1, Dec. 8, 2016
Int. Cl. H01L 27/1156 (2017.01); H01L 27/108 (2006.01); H01L 21/84 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2017.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 29/786 (2006.01); C23C 14/08 (2006.01); H01L 27/06 (2006.01); H01L 27/11507 (2017.01); H01L 27/11514 (2017.01)
CPC H01L 27/1085 (2013.01) [C23C 14/08 (2013.01); H01L 21/84 (2013.01); H01L 27/105 (2013.01); H01L 27/10885 (2013.01); H01L 27/10891 (2013.01); H01L 27/115 (2013.01); H01L 27/1203 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 28/40 (2013.01); H01L 29/7869 (2013.01); H01L 29/78642 (2013.01); H01L 27/0688 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/1156 (2013.01); H01L 27/11507 (2013.01); H01L 27/11514 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising steps of:
forming a bit line over an insulating surface;
forming a semiconductor layer over the bit line, the semiconductor layer being prism-shaped or cylinder-shaped, and comprising a semiconductor material having a wider band gap than silicon;
forming a gate insulating layer covering the bit line and the semiconductor layer;
forming a word line covering at least part of a side face of the semiconductor layer with the gate insulating layer interposed therebetween;
removing a part of the gate insulating layer so as to expose a top surface of the semiconductor layer;
forming a capacitor electrode in contact with the top surface of the semiconductor layer; and
stacking, in that order, an insulating layer and a capacitor line over the capacitor electrode,
wherein a top surface of the semiconductor layer, a top surface of the gate insulating layer, and a top surface of the word line are in a same horizontal plane.