US 9,812,457 B1
Ultra high density integrated composite capacitor
Ramesh Harjani, Minneapolis, MN (US); Rakesh Kumar Palani, Tustin, CA (US); and Saurabh Chaubey, Minneapolis, MN (US)
Assigned to REGENTS OF THE UNIVERSITY OF MINNESOTA, Minneapolis, MN (US)
Filed by Regents of the University of Minnesota, Minneapolis, MN (US)
Filed on Apr. 19, 2016, as Appl. No. 15/132,326.
Int. Cl. H01L 21/00 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/146 (2006.01); H01L 27/12 (2006.01); H01L 27/08 (2006.01)
CPC H01L 27/10805 (2013.01) [H01L 28/40 (2013.01); H01L 27/0805 (2013.01); H01L 27/1255 (2013.01); H01L 27/14689 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip comprising:
a metal-oxide-silicon (MOS) capacitor comprising a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal,
wherein the drain terminal and the source terminal are not electrically connected to any other node within the IC chip so as to be electrically floating within the IC chip, and
wherein the gate terminal and the body terminal of the MOS transistor form respective first and second terminals of the MOS capacitor;
a first conductor coupled to the gate terminal; and
a second conductor coupled to the body terminal,
wherein the first and second conductors set a potential at the gate terminal relative to a potential at the body terminal to configure and operate the MOS capacitor in an accumulation mode.