US 9,812,456 B2
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
Yuniarto Widjaja, San Jose, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Jan. 24, 2017, as Appl. No. 15/414,009.
Application 15/414,009 is a division of application No. 14/563,133, filed on Dec. 8, 2014, granted, now 9,589,963.
Application 14/563,133 is a continuation of application No. 14/282,850, filed on May 20, 2014, granted, now 8,934,296.
Application 14/282,850 is a continuation of application No. 14/046,986, filed on Oct. 6, 2013, granted, now 8,767,458.
Application 14/046,986 is a continuation of application No. 13/296,402, filed on Nov. 15, 2011, granted, now 8,582,359.
Claims priority of provisional application 61/413,992, filed on Nov. 16, 2010.
Prior Publication US 2017/0133382 A1, May 11, 2017
Int. Cl. G11C 11/34 (2006.01); H01L 27/108 (2006.01); H01Q 1/22 (2006.01); G11C 7/00 (2006.01); H01L 27/102 (2006.01)
CPC H01L 27/10802 (2013.01) [G11C 7/00 (2013.01); H01L 27/1023 (2013.01); H01Q 1/2283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-port semiconductor memory cell comprising:
a plurality of gates;
a common body region insulated from said plurality of gates and of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and
a plurality of conductive regions of a second conductivity type,
wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;
wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and
wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.