| US 9,812,455 B2 | ||
| Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias | ||
| Sanh D. Tang, Kuna, ID (US); Wolfgang Mueller, Garden City, ID (US); Brent Gilgen, Boise, ID (US); Dylan R. Macmaster, Boise, ID (US); and Jim A. Jozwiak, Boise, ID (US) | ||
| Assigned to Micron Technology, Inc., Boise, ID (US) | ||
| Filed by Micron Technology, Inc., Boise, ID (US) | ||
| Filed on Jul. 25, 2016, as Appl. No. 15/218,487. | ||
| Application 15/218,487 is a division of application No. 14/307,121, filed on Jun. 17, 2014, granted, now 9,589,962. | ||
| Prior Publication US 2016/0336325 A1, Nov. 17, 2016 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01); H01L 21/3213 (2006.01) | ||
| CPC H01L 27/108 (2013.01) [H01L 21/32133 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 27/10855 (2013.01); H01L 28/60 (2013.01); H01L 28/90 (2013.01); H01L 21/76885 (2013.01)] | 17 Claims |
| 1. An array of conductive vias, comprising:
spaced line constructions individually comprising a dielectric top and dielectric sidewalls; and
conductive vias extending elevationally between immediately adjacent of the line constructions, the conductive vias individually
comprising an elevationally inner conductive material and an elevationally outer conductive material of different composition
from composition of the elevationally inner conductive material, the elevationally inner conductive material being laterally
recessed from the elevationally outer conductive material on at least one side of an individual conductive via of the conductive
vias in at least one straight line vertical cross section.
|