US 9,812,454 B2
Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal cathode lines
Harry Luan, Saratoga, CA (US); Valery Axelrad, Woodside, CA (US); and Charlie Cheng, Los Altos, CA (US)
Assigned to Kilopass Technology, Inc., San Jose, CA (US)
Filed by Kilopass Technology, Inc., San Jose, CA (US)
Filed on Jun. 30, 2016, as Appl. No. 15/199,934.
Claims priority of provisional application 62/300,015, filed on Feb. 25, 2016.
Claims priority of provisional application 62/292,547, filed on Feb. 8, 2016.
Claims priority of provisional application 62/294,239, filed on Feb. 11, 2016.
Claims priority of provisional application 62/294,270, filed on Feb. 11, 2016.
Prior Publication US 2017/0229465 A1, Aug. 10, 2017
Int. Cl. H01L 29/74 (2006.01); H01L 27/102 (2006.01); H01L 23/532 (2006.01); H01L 29/45 (2006.01); H01L 21/8229 (2006.01); H01L 21/285 (2006.01)
CPC H01L 27/1027 (2013.01) [H01L 21/28518 (2013.01); H01L 21/28525 (2013.01); H01L 21/28562 (2013.01); H01L 21/28568 (2013.01); H01L 21/8229 (2013.01); H01L 23/53209 (2013.01); H01L 23/53242 (2013.01); H01L 29/456 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A plurality of volatile memory cells comprising:
a first silicon thyristor comprising a first cathode formed from a first material;
a second silicon thyristor comprising a second cathode formed from the first material;
a first cathode line, formed from a conductor material, connecting the first cathode of the first silicon thyristor and the second cathode of the second silicon thyristor, and wherein a minority carrier lifetime of a minority carrier is shorter in the conductor material than in the first material; and
a first isolation insulator region separating a first portion of the first silicon thyristor and a second portion of the second silicon thyristor.