US 9,812,453 B1
Self-aligned sacrificial epitaxial capping for trench silicide
George R. Mulfinger, Gansevoort, NY (US); Lakshmanan H. Vanamurthy, Saratoga Springs, NY (US); Scott Beasor, Greenwich, NY (US); Timothy J. McArdle, Ballston Lake, NY (US); Judson R. Holt, Ballston Lake, NY (US); and Hao Zhang, Clifton Park, NY (US)
Assigned to GLOBALFOUNDRIES INC., Grand Cayman (KY)
Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed on Feb. 13, 2017, as Appl. No. 15/431,334.
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01); H01L 29/167 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method comprising:
forming a silicon (Si) fin in a p-channel field-effect transistor (PFET) region and a pair of Si fins in a n-channel field-effect transistor (NFET) region;
forming epitaxial source/drain (S/D) regions on ends of the Si fins;
forming a spacer over the epitaxial S/D region in the PFET region;
forming a sacrificial cap over the epitaxial S/D regions in the NFET region, merging the pair of Si fins;
removing the spacer from the epitaxial S/D region in the PFET region;
forming silicide trenches over the epitaxial S/D regions in the PFET and NEFT regions;
implanting dopant into the epitaxial S/D region in the PFET region while the sacrificial cap protects the epitaxial S/D regions in the NFET region;
removing the sacrificial cap; and
forming a metal layer over top surfaces of the epitaxial S/D region in the PFET region and top and bottom surfaces of the epitaxial S/D regions in the NFET region.