US 9,812,449 B2
Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
Borna J. Obradovic, Leander, TX (US); Titash Rakshit, Austin, TX (US); Mark S. Rodder, Dallas, TX (US); and Wei-E Wang, Austin, TX (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR)
Filed on May 18, 2016, as Appl. No. 15/158,459.
Claims priority of provisional application 62/258,400, filed on Nov. 20, 2015.
Prior Publication US 2017/0148787 A1, May 25, 2017
Int. Cl. H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 29/0665 (2013.01); H01L 29/20 (2013.01); H01L 29/4232 (2013.01); H01L 29/4916 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field effect transistor, comprising:
a channel comprising, as a major component, a first III-V semiconductor material;
a dielectric layer directly on the channel; and
a semiconductor gate layer, the dielectric layer being between the semiconductor gate layer and the channel, the semiconductor gate layer comprising, as a major component, a noncrystalline semiconductor,
wherein the semiconductor gate layer comprises, as a major component, InxP1-xN, wherein x is between 0.1 and 0.9.