US 9,812,443 B1
Forming vertical transistors and metal-insulator-metal capacitors on the same chip
Kangguo Cheng, Schenectady, NY (US); Ruilong Xie, Schenectady, NY (US); Tenko Yamashita, Schenectady, NY (US); and Chun-Chen Yeh, Clifton Park, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jan. 13, 2017, as Appl. No. 15/405,433.
Int. Cl. H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 49/02 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 21/308 (2013.01); H01L 21/30604 (2013.01); H01L 21/823487 (2013.01); H01L 28/60 (2013.01); H01L 29/42392 (2013.01); H01L 29/78642 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of fabricating a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate, the method comprising:
forming a first vertical transistor and a second vertical transistor on the substrate, the first vertical transistor and the second vertical transistor each comprising a bottom source/drain, a fin channel extending vertically from the bottom source/drain to a top source/drain, and a gate arranged around the fin channel, and the gate comprising a dielectric layer and a gate metal;
depositing a mask on the first vertical transistor and the second vertical transistor;
patterning the mask to expose the top source/drain of the second vertical transistor;
removing the top source/drain, the fin channel, and a portion of the bottom source/drain of the second vertical transistor; and
depositing a metal directly onto the gate of the second vertical transistor to form the MIM capacitor adjacent to the first vertical transistor, the metal directly contacting the dielectric layer of the gate and extending from the bottom source/drain, through the gate, and to a surface of the mask.
 
9. A method of fabricating a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate, the method comprising:
forming a first vertical transistor and a second vertical transistor on the substrate, the first vertical transistor and the second vertical transistor each comprising a bottom source/drain, a fin channel extending vertically from the bottom source/drain to a top source/drain, and a gate arranged around the fin channel, and the gate comprising a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate;
depositing a mask on the first vertical transistor and the second vertical transistor;
patterning the mask to expose the top source/drain of the second vertical transistor;
removing the top source/drain, the fin channel, a portion of the bottom source/drain, and the spacers of the second vertical transistor;
removing and replacing the dielectric layer of the gate of the second vertical transistor with a thicker dielectric layer; and
depositing a metal directly onto the thicker dielectric layer to form the MIM capacitor adjacent to the first vertical transistor.