US 9,812,442 B2
Integrated semiconductor device and manufacturing method therefor
Zhongshan Hong, Beijing (CN)
Filed by Zhongshan Hong, Beijing (CN)
Filed on Mar. 12, 2012, as Appl. No. 13/418,339.
Claims priority of application No. 2011 1 0410241 (CN), filed on Dec. 12, 2011.
Prior Publication US 2013/0146989 A1, Jun. 13, 2013
Int. Cl. H01L 27/06 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01L 21/283 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 27/0802 (2013.01); H01L 28/24 (2013.01)] 14 Claims
OG exemplary drawing
1. An integrated semiconductor device comprising:
a field effect transistor formed within and on an active region of a semiconductor substrate;
a resistor formed on an isolation region of the semiconductor substrate; and
an interlayer dielectric layer,
wherein the field effect transistor comprises a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer that are sequentially stacked on the semiconductor substrate, the dielectric layer being on the semiconductor substrate and the first conductive layer being sandwiched between the dielectric layer and the second conductive layer;
wherein the resistor comprises a resistor body being an enclosure portion of the first conductive layer entirely on the dielectric layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body, wherein the enclosure portion comprises two linear segments extending between the distal ends of the resistor body, a resistance of the resistor body defining a resistance value of the resistor; and
wherein the interlayer dielectric layer extends between the resistor terminals and into an opening in the enclosure portion to directly contact a portion of the dielectric layer through the opening in the enclosure portion, the interlayer dielectric layer direct contacting the enclosure portion, the opening in the enclosure portion being entirely surrounded by and between the two linear segments and the distal ends of the resistor body, inner and outer perimeters of the enclosure portion formed by the first conducitve layer being continuous in a plan view, the outer perimeter of the enclosure portion being co-aligned with an outer perimeter of the resistor terminals.