US 9,812,441 B2
Semiconductor integrated circuit device
Koichi Taniguchi, Kyoto (JP); and Masato Maede, Kyoto (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Jan. 10, 2017, as Appl. No. 15/402,952.
Application 12/786,090 is a division of application No. 11/966,529, filed on Dec. 28, 2007, granted, now 7,750,373, issued on Jul. 6, 2010.
Application 15/402,952 is a continuation of application No. 15/147,555, filed on May 5, 2016, granted, now 9,576,947.
Application 15/147,555 is a continuation of application No. 14/684,323, filed on Apr. 10, 2015, granted, now 9,379,101, issued on Jun. 28, 2016.
Application 14/684,323 is a continuation of application No. 14/276,940, filed on May 13, 2014, granted, now 9,029,917, issued on May 12, 2015.
Application 14/276,940 is a continuation of application No. 12/786,090, filed on May 24, 2010, granted, now 8,759,883, issued on Jun. 24, 2014.
Claims priority of application No. 2006-354397 (JP), filed on Dec. 28, 2006.
Prior Publication US 2017/0117268 A1, Apr. 27, 2017
Int. Cl. H01L 27/02 (2006.01); H01L 23/50 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/0292 (2013.01) [H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/0928 (2013.01); H01L 29/0623 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device, comprising:
a semiconductor chip including an internal circuit and a plurality of I/O cells, wherein:
the plurality of I/O cells are provided on a periphery area of the semiconductor chip,
each of the plurality of I/O cells includes a first region to which first voltage is supplied and a second region to which second voltage is supplied, wherein the second voltage is lower than the first voltage, the first region including a protective circuit,
the first region is disposed closer to an outermost edge of the semiconductor chip than the second region,
each of the plurality of I/O cells has a corresponding electrode pad overlapping the I/O cell in plan view and connected to the corresponding protective circuit,
electrode pads of the plurality of I/O cells are arranged on a first line and a second line, the first line being disposed closer to the outermost edge of the semiconductor chip than the second line, and
the protective circuit of each of the plurality of I/O cells includes:
a power source-side protective circuit provided between the corresponding electrode pad and a power source wiring; and
a ground-side protective circuit provided between the corresponding electrode pad and a ground wiring,
the power source-side protective circuit is positioned closer to the outermost edge of the semiconductor chip than the ground-side protective circuit, and
at least one of the power source-side protective circuit and the ground-side protective circuit has a guard ring.