US 9,812,440 B2
Biased ESD circuit
Kenneth P. Snowdon, Falmouth, ME (US); Taeghyun Kang, Scarborough, ME (US); and Yongliang Li, Beijing (CN)
Assigned to Fairchild Semiconductor Corporation, San Jose, CA (US)
Filed by Fairchild Semiconductor Corporation, San Jose, CA (US)
Filed on Aug. 25, 2015, as Appl. No. 14/834,554.
Claims priority of provisional application 62/043,873, filed on Aug. 29, 2014.
Prior Publication US 2016/0064374 A1, Mar. 3, 2016
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01)
CPC H01L 27/0266 (2013.01) [H02H 9/046 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A biased electrostatic discharge (ESD) circuit, comprising:
an ESD device including a gate terminal, a source terminal, a drain terminal, and a bulk terminal, wherein the ESD device is configured to provide an ESD discharge path between the drain terminal and the source terminal; and
at least one three-terminal resistor coupled between the gate terminal of the ESD device and the bulk terminal of the ESD device, the at least one three-terminal resistor having a gate terminal coupled to ground,
wherein the bulk terminal of the ESD device is configured to receive negative bias to reduce the drain terminal to source terminal capacitance of the ESD device.