US 9,812,437 B2 | ||
Semiconductor integrated circuit device, and electronic appliance using the same | ||
Hideyuki Kakubari, Shiojiri (JP) | ||
Assigned to SEIKO EPSON CORPORATION, Tokyo (JP) | ||
Filed by SEIKO EPSON CORPORATION, Tokyo (JP) | ||
Filed on Feb. 25, 2015, as Appl. No. 14/631,079. | ||
Claims priority of application No. 2014-035050 (JP), filed on Feb. 26, 2014; and application No. 2015-033787 (JP), filed on Feb. 24, 2015. | ||
Prior Publication US 2015/0243646 A1, Aug. 27, 2015 | ||
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01); H01L 29/74 (2006.01); H01L 27/092 (2006.01) |
CPC H01L 27/0255 (2013.01) [H01L 27/0292 (2013.01); H01L 29/7412 (2013.01); H01L 27/092 (2013.01)] | 6 Claims |
1. A semiconductor integrated circuit device comprising:
a first power supply terminal to which a first power supply potential is supplied;
a second power supply terminal to which a second power supply potential that is lower than the first power supply potential
is supplied;
a signal terminal that at least outputs a signal;
an output buffer circuit including a P channel transistor connected between the first power supply terminal and the signal
terminal, and an N channel transistor connected between the signal terminal and the second power supply terminal;
a potential control circuit that supplies the potential of the first power supply terminal or a potential of the signal terminal
to a back gate of the P channel transistor according to the potential of the signal terminal;
a first protection diode including an anode connected to the signal terminal;
a common discharge line connected to a cathode of the first protection diode;
an electrostatic discharge protection circuit connected between the common discharge line and the second power supply terminal;
and
a second protection diode including an anode connected to the second power supply terminal, and a cathode connected to the
signal terminal.
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