US 9,812,436 B2
SCRs with checker board layouts
Yu-Ti Su, Tainan (TW); Wun-Jie Lin, Hsin-Chu (TW); Han-Jen Yang, Taipei (TW); Shui-Ming Cheng, Zhubei (TW); and Ming-Hsiang Song, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Sep. 3, 2015, as Appl. No. 14/844,272.
Application 14/844,272 is a continuation of application No. 14/044,601, filed on Oct. 2, 2013, granted, now 9,147,676.
Prior Publication US 2015/0380396 A1, Dec. 31, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/74 (2006.01); H01L 27/08 (2006.01)
CPC H01L 27/0248 (2013.01) [H01L 27/0262 (2013.01); H01L 27/0629 (2013.01); H01L 27/0647 (2013.01); H01L 27/0814 (2013.01); H01L 29/7436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An Electro-Static Discharge (ESD) protection circuit comprising:
a first semiconductor strip in a first well, the first semiconductor strip extending along a first row direction, the first semiconductor strip having a first p-doped portion and a first n-doped portion;
a second semiconductor strip in a second well, the first well and the second well being physically separated and having a same conductivity type, the first well and the second well being in a third well having a different conductivity type, the second semiconductor strip extending along a second row direction parallel to the first row direction, the second semiconductor strip having a second p-doped portion and a second n-doped portion, the first p-doped portion and the second n-doped portion being aligned along a first column direction, the first n-doped portion and the second p-doped portion being aligned along a second column direction parallel to the first column direction; and
a conductor electrically connecting the first n-doped portion to the second p-doped portion.
 
7. An Electro-Static Discharge (ESD) protection circuit comprising:
a substrate having a first doped region of a first dopant type and having a second doped region in the first doped region, a third doped region in the first doped region, a fourth doped region in the first doped region, and a fifth doped region in the first doped region, each of the second doped region, the third doped region, the fourth doped region, and the fifth doped region being of a second dopant type opposite from the first dopant type, the second doped region, the third doped region, the fourth doped region, and the fifth doped region being physically separated from each other, the first dopant type being N type or P type, the second dopant type being N type or P type;
a first semiconductor strip on the second doped region, the first semiconductor strip having a sixth doped region of a third dopant type, the third dopant type being N type or P type;
a second semiconductor strip on the third doped region, the second semiconductor strip having a seventh doped region of a fourth dopant type opposite from the third dopant type, the fourth dopant type being N type or P type;
a third semiconductor strip on the fourth doped region, the third semiconductor strip having an eighth doped region of the third dopant type;
a fourth semiconductor strip on the fifth doped region, the fourth semiconductor strip having a ninth doped region of the fourth dopant type; and
a first electrical connection connecting the seventh doped region of the second semiconductor strip to the eighth doped region of the third semiconductor strip.
 
14. A circuit comprising:
an Electro-Static Discharge (ESD) protection circuit comprising:
a Silicon-Controlled Rectifier (SCR)/diode-string combination unit electrically coupled between a first node and a second node, the SCR/diode-string combination unit comprising:
a first doped region and a second doped region in a first semiconductor strip, the first doped region and the second doped region being doped opposite dopant types, a p-n junction of a first diode being formed between the first doped region and the second doped region, the first semiconductor strip being in a first doped well region,
a third doped region and a fourth doped region in a second semiconductor strip, the third doped region and the fourth doped region being doped opposite dopant types, a p-n junction of a second diode being formed between the third doped region and the fourth doped region, the second semiconductor strip being in a second doped well region, the first doped well region and the second doped well region being disposed in a third doped well region, each of the first doped well region and the second doped well region being doped an opposite dopant type from the third doped well region, and
an electrical connection connecting the second doped region to the fourth doped region; and
a diode-string-free SCR unit electrically coupled between the first node and the second node, no diode string being between the first node and the second node in the diode-string-free SCR unit, the diode-string-free SCR unit comprising:
a fifth doped region in the first semiconductor strip, and
a sixth doped region in the second semiconductor strip, the fifth doped region and the sixth doped region being doped opposite dopant types.