US 9,812,435 B2
Semiconductor device
Takeshi Okagaki, Tokyo (JP); Koji Shibutani, Tokyo (JP); Makoto Yabuuchi, Tokyo (JP); and Nobuhiro Tsuda, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Koutou-ku (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Aug. 14, 2015, as Appl. No. 14/826,730.
Claims priority of application No. 2014-166157 (JP), filed on Aug. 18, 2014; and application No. 2015-067882 (JP), filed on Mar. 30, 2015.
Prior Publication US 2016/0049395 A1, Feb. 18, 2016
Int. Cl. H01L 27/088 (2006.01); H01L 27/02 (2006.01); G06F 17/50 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 17/5077 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a rectangular parallelepiped first fin extending in a first direction;
a rectangular parallelepiped second fin arranged to be separated from the first fin and extending in the first direction;
a gate electrode arranged on the first fin and the second fin through a gate insulating film and extending in a second direction crossing the first direction;
a first electrode of a first transistor formed in the first fin positioned on one side of the gate electrode;
a second electrode of the first transistor formed in the first fin positioned on the other side of the gate electrode;
a first electrode of a second transistor formed in the second fin positioned on the one side of the gate electrode;
a second electrode of the second transistor formed in the second fin positioned on the other side of the gate electrode;
a first local wiring for connecting the first electrode of the first transistor and the first electrode of the second transistor,
wherein the first local wiring is made of a conductive film buried in an interlayer insulating film covering the gate electrode and includes:
a first portion extending in the first direction and electrically connected to the first electrode of the first transistor;
a second portion extending in the first direction and electrically connected to the first electrode of the second transistor; and
a third portion extending in the second direction and connecting the first portion and the second portion,
a dummy gate arranged to be separated from the gate electrode and extending in the second direction,
wherein the dummy gate is positioned below the first portion and the second portion, and
a second local wiring extending in the second direction and connected to the second electrode of the first transistor,
wherein the second local wiring is connected to a wiring to which a source potential is applied.