US 9,812,429 B2
Interconnect structures for assembly of multi-layer semiconductor devices
Rabindra N. Das, Lexington, MA (US); Mark A. Gouker, Belmont, MA (US); Pascale Gouker, Lexington, MA (US); Leonard M. Johnson, Carlisle, MA (US); and Ryan C. Johnson, Woburn, MA (US)
Assigned to MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Cambridge, MA (US)
Appl. No. 15/312,063
Filed by Massachusetts Institute of Technology, Cambridge, MA (US)
PCT Filed Nov. 5, 2015, PCT No. PCT/US2015/059200
§ 371(c)(1), (2) Date Nov. 17, 2016,
PCT Pub. No. WO2016/118210, PCT Pub. Date Jul. 28, 2016.
Claims priority of provisional application 62/075,318, filed on Nov. 5, 2014.
Prior Publication US 2017/0092621 A1, Mar. 30, 2017
Int. Cl. H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A multi-layer semiconductor device comprising:
a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch;
a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch;
a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch;
one or more first interconnect structures disposed between and coupled to first select portions of the first surface of the second semiconductor structure and to first select portions of the second surface of the first semiconductor structure to form an interconnect for electrically and mechanically coupling the second semiconductor structure to the first semiconductor structure, each of the first interconnect structures having first and second opposing portions, wherein a distance between the first and second portions is selected based upon at least one of the first semiconductor package pitch and the second semiconductor package pitch; and
one or more second interconnect structures disposed between and coupled to first select portions of the first surface of the third semiconductor structure and to second select portions of the second surface of the first semiconductor structure to form an interconnect for electrically and mechanically coupling the third semiconductor structure to the first semiconductor structure, each of the second interconnect structures having first and second opposing portions, wherein a distance between the first and second portions is selected based upon at least one of the first semiconductor package pitch and the third semiconductor package pitch, and the first and second interconnect structures are selected such that second semiconductor structure is provided on a same package level of the multi-layer semiconductor device as the third semiconductor structure;
wherein at least one of the first interconnect structures comprises:
a first interconnect structure portion coupled to the second surface of first semiconductor structure, including:
a first interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the first portion of the at least one of the first interconnect structures; and
a first conductive structure having first and second opposing surfaces and one or more sides, the first surface disposed over and coupled to the second surface of the first interconnect pad, and the second surface and select ones of the sides coated with a first fusible conductive material having a first melt temperature; and
a second interconnect structure portion coupled to the first surface of second semiconductor structure, including:
a second interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the second portion of the at least one of the first interconnect structures; and
a second conductive structure having first and second opposing surfaces and one or more sides, the first surface disposed over and coupled to the second surface of the second interconnect pad and wherein the second surface and select ones of the sides of the second conductive structure are coated with a second fusible conductive material having a second, different melt temperature; and
an under bump metallization (UBM) layer or structure disposed between the first surface of the second conductive structure and the second surface of the second interconnect pad, the UBM layer or structure provided from a third fusible conductive material having a third, different melt temperature.