US 9,812,428 B2
Vertically integrated wafers with thermal dissipation
Zhijiong Luo, Poughkeepsie, NY (US)
Assigned to EMPIRE TECHNOLOGY DEVELOPMENT LLC, Wilmington, DE (US)
Filed by Empire Technology Development LLC, Wilmington, DE (US)
Filed on Oct. 21, 2016, as Appl. No. 15/299,483.
Application 15/299,483 is a division of application No. 14/445,991, filed on Jul. 29, 2014, granted, now 9,508,685.
Prior Publication US 2017/0040295 A1, Feb. 9, 2017
Int. Cl. H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/822 (2006.01); H01L 23/34 (2006.01); H01L 23/36 (2006.01); H01L 21/18 (2006.01); H01L 23/532 (2006.01); H01L 21/60 (2006.01); H01L 21/768 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/187 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/8221 (2013.01); H01L 23/34 (2013.01); H01L 23/36 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/75 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 21/76889 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 2021/60007 (2013.01); H01L 2021/60097 (2013.01); H01L 2224/2745 (2013.01); H01L 2224/27452 (2013.01); H01L 2224/27614 (2013.01); H01L 2224/27848 (2013.01); H01L 2224/291 (2013.01); H01L 2224/2918 (2013.01); H01L 2224/29124 (2013.01); H01L 2224/29138 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/29155 (2013.01); H01L 2224/29166 (2013.01); H01L 2224/29181 (2013.01); H01L 2224/29184 (2013.01); H01L 2224/32113 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32147 (2013.01); H01L 2224/32503 (2013.01); H01L 2224/7525 (2013.01); H01L 2224/838 (2013.01); H01L 2224/83048 (2013.01); H01L 2224/83895 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01042 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/048 (2013.01); H01L 2924/0474 (2013.01); H01L 2924/0475 (2013.01); H01L 2924/0476 (2013.01); H01L 2924/0481 (2013.01); H01L 2924/0483 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/20641 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A three-dimensionally integrated semiconductor device, comprising:
a first wafer that includes a first set of semiconductor circuitry;
a second wafer that includes a second set of semiconductor circuitry;
silicide layers located between conductive coupler surfaces of the first wafer and the second wafer,
wherein the silicide layers are effective to bond the first wafer and the second wafer, and
wherein the silicide layers are effective to provide heat dissipation for the first set of semiconductor circuitry and the second set of semiconductor circuitry through gaps between the silicide layers; and
portions of an amorphous silicon layer or a porous silicon layer located between at least two of the silicide layers.