US 9,812,426 B1
Integrated fan-out package, semiconductor device, and method of fabricating the same
Chin-Te Wang, Taipei (TW); Cheng-Hsien Hsieh, Kaohsiung (TW); Hsien-Wei Chen, Hsinchu (TW); Li-Han Hsu, Hsin-Chu (TW); Tzu-Shiun Sheu, Hsinchu (TW); Wei-Cheng Wu, Hsinchu (TW); and Yan-Fu Lin, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 7, 2016, as Appl. No. 15/257,920.
Claims priority of provisional application 62/356,511, filed on Jun. 29, 2016.
Int. Cl. H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/02 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01); H01L 2224/0221 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/113 (2013.01); H01L 2224/13018 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13027 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated fan-out package, comprising:
a semiconductor device comprising an integrated circuit component having a plurality of conductive pads, a protection layer covering the integrated circuit component, and a plurality of conductive vias, wherein the protection layer comprises a plurality of contact openings located above the conductive pads, the conductive vias are embedded in the contact openings of the protection layer and electrically connected to the conductive pads through the contact openings of the protection layer, and top surfaces of the conductive vias are substantially coplanar with a top surface of the protection layer;
an insulating encapsulation laterally encapsulating sidewalls of the semiconductor device, wherein the conductive vias and the insulating encapsulation are spaced apart by the protection layer, and the top surfaces of the conductive vias are substantially coplanar with a top surface of the insulating encapsulation; and
a redistribution circuit structure disposed on top surfaces of the conductive vias, the top surface of the protection layer and a top surface of the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the conductive vias.