US 9,812,425 B2
Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
Bok Eng Cheah, Bayan Lepas (MY); Shanggar Periaman, Penang (MY); Kooi Chi Ooi, Bayan Lepas (MY); and Jackson Chung Peng Kong, Bayan Lepas (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 28, 2016, as Appl. No. 15/278,532.
Application 15/278,532 is a continuation of application No. 14/852,013, filed on Sep. 11, 2015, granted, now 9,478,524, issued on Oct. 25, 2016.
Application 14/852,013 is a continuation of application No. 13/997,041, granted, now 9,136,251, issued on Sep. 15, 2015, previously published as PCT/MY2012/000191, filed on Jun. 25, 2012.
Prior Publication US 2017/0018530 A1, Jan. 19, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 24/13 (2013.01); H01L 24/80 (2013.01); H01L 24/81 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/06183 (2013.01); H01L 2224/06189 (2013.01); H01L 2224/06517 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16137 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17183 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80894 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/351 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a main stacked dies (MSD) structure comprising a substantially horizontal arrangement of semiconductor dies interconnected to the substrate;
a vertical side chip electrically coupled to a side of the MSD structure, wherein the vertical side chip comprises one or more through silicon vias (TSVs); and
an underfill material disposed between the substrate and the MSD structure, wherein the underfill material is further disposed between the substrate and the vertical side chip.