US 9,812,416 B2
Semiconductor arrangement and formation thereof
Jiun Yi Wu, Zhongli (TW); Hsueh-Lung Cheng, Hsinchu (TW); and Shou-Yi Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on May 8, 2017, as Appl. No. 15/589,027.
Application 15/589,027 is a division of application No. 14/208,310, filed on Mar. 13, 2014, granted, now 9,646,928.
Prior Publication US 2017/0243842 A1, Aug. 24, 2017
Int. Cl. H01L 21/4763 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01)
CPC H01L 24/03 (2013.01) [H01L 21/7685 (2013.01); H01L 21/76804 (2013.01); H01L 21/76879 (2013.01); H01L 22/32 (2013.01); H01L 23/5226 (2013.01); H01L 24/06 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05147 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor arrangement, comprising:
depositing a metal over an initial dielectric layer to form a metal trace;
depositing a first dielectric material over the metal trace to form a first dielectric layer;
etching the first dielectric layer to form a first opening within which a first via is formed, wherein the first via is coupled to the metal trace;
depositing a second dielectric material over the first via and the first dielectric layer to form a second dielectric layer;
etching the second dielectric layer to form a second opening within which a second via is formed, wherein the second via is coupled to the first via;
etching the first dielectric layer and the second dielectric layer to form a third opening;
depositing upper test metal material to form an upper test metal layer overlying the first dielectric layer and the second dielectric layer; and
plating the third opening to form a test pad metal layer lining the third opening and extending from the upper test metal layer through the first dielectric layer and the second dielectric layer, wherein the metal trace is in contact with a sidewall of the test pad metal layer.