US 9,812,414 B1
Chip package and a manufacturing method thereof
Po Chun Lin, Changhua (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, Taoyuan (TW)
Filed by NANYA TECHNOLOGY CORPORATION, Taoyuan (TW)
Filed on Jun. 17, 2016, as Appl. No. 15/186,100.
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 24/02 (2013.01) [H01L 23/5389 (2013.01); H01L 24/13 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/02165 (2013.01); H01L 2224/02185 (2013.01); H01L 2224/02315 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/13024 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/35121 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A chip package comprising:
a first substrate;
a first insulation layer disposed over the first substrate;
a conductive structure disposed within the first insulation layer;
a buffering member embedded into the first insulation layer;
a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and
a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member,
wherein a width of the buffering member is substantially equal to a width of the portion of the RDL exposed from the second insulation layer,
wherein a thickness of the buffering member is about 0.05 μm to about 5 μm, and
wherein the buffering member includes elastic, flexible or soft material.