US 9,812,409 B2
Seal ring structure with a metal pad
Jeng-Shyan Lin, Tainan (TW); Dun-Nian Yaung, Taipei (TW); Jen-Cheng Liu, Hsin-Chu (TW); Hsin-Hui Lee, Kaohsiung (TW); Wen-De Wang, Minsyong Township (TW); and Shu-Ting Tsai, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 18, 2015, as Appl. No. 14/715,087.
Application 13/624,938 is a division of application No. 12/916,789, filed on Nov. 1, 2010, granted, now 8,283,754, issued on Oct. 9, 2012.
Application 14/715,087 is a continuation of application No. 13/624,938, filed on Sep. 23, 2012, granted, now 9,035,445.
Claims priority of provisional application 61/373,634, filed on Aug. 13, 2010.
Prior Publication US 2015/0249057 A1, Sep. 3, 2015
Int. Cl. H01L 23/58 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01); H01L 21/02 (2006.01); H01L 23/488 (2006.01); H01L 21/306 (2006.01); H01L 21/31 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 21/02697 (2013.01); H01L 21/30604 (2013.01); H01L 21/31 (2013.01); H01L 21/31111 (2013.01); H01L 21/32051 (2013.01); H01L 21/6835 (2013.01); H01L 21/76 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/488 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 27/1464 (2013.01); H01L 27/14618 (2013.01); H01L 27/14636 (2013.01); H01L 24/06 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68304 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68363 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/03 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06181 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a seal ring structure over a first side of a semiconductor substrate;
forming a first passivation layer over the first side of the semiconductor substrate;
forming a first metal pad over the first passivation layer on the first side of the semiconductor substrate, wherein the first metal pad includes a recess;
forming a second passivation layer directly on the first metal pad and within the recess;
after forming the second passivation layer directly on the first metal pad and within the recess, bonding a carrier wafer to the second passivation layer; and
forming a second metal pad over a second side of the semiconductor substrate that is opposite the first side of the semiconductor substrate
reducing a thickness of the semiconductor substrate after forming the first metal pad over the first side of the semiconductor substrate; and
after reducing the thickness of the semiconductor substrate, forming a trench through the semiconductor substrate that extends from the second side of the semiconductor substrate, through the first side of the semiconductor substrate and to the seal ring structure formed over the first side of the semiconductor substrate.